?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b rfd20n03, RFD20N03SM 20a, 30v, 0.025 ohm, n-channel power mosfets the rfd20n03 and RFD20N03SM n-channel power mosfets are manufactured using the megafet process. this process which uses feature sizes approaching those of lsi integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. these transistors can be operated directly from integrated circuits. formerly developmental type ta49235. features 20a, 30v ? ds(on) = 0.025 ? temperature compensating pspice model thermal impedance spice model peak current vs pulse width curve uis rating curve 175 o c operating temperature related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-251aa jedec to-252aa ordering information part number package brand rfd20n03 to-251aa f20n03 RFD20N03SM to-252aa f20n03 note: when ordering, use the entire part number. add the suf? 9a to obtain the to-252aa variant in tape and reel, e.g., RFD20N03SM9a. d g s drain (flange) drain source gate drain (flange) gate source data sheet january 2002
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d units drain to source voltage (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 20 figure 5 a pulsed avalanche rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e as figure 6 power dissipation (figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d derate above 25 o c (figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0.60 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 30 - - v gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 2 - 4 v zero gate voltage drain current i dss v ds = 30v, v gs = 0v - - 1 a v ds = 30v, v gs = 0v, t c = 150 o c--50 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance r ds(on) i d = 20a, v gs = 10v (figure 9) - 0.022 0.025 ? turn-on time t on v dd = 15v, i d ? 20a, r l =0.75 ? , v gs = 10v, r gs = 9.1 ? - - 60 ns turn-on delay time t d(on) -10-ns rise time t r -30-ns turn-off delay time t d(off) -12-ns fall time t f -32-ns turn-off time t off - - 66 ns total gate charge q g(tot) v gs = 0v to 20v v dd = 15v, i d ? 20a, r l = 0.75 ? i g(ref) = 1.0ma (figure 13) -6075nc gate charge at 10v q g(10) v gs = 0v to 10v - 28 40 nc threshold gate charge q g(th) v gs = 0v to 2v - 2.4 2.9 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 1150 - pf output capacitance c oss - 550 - pf reverse transfer capacitance c rss - 110 - pf thermal resistance junction to case r jc (figure 3) - - 1.66 o c/w thermal resistance junction to ambient r ja to-251, to-252 - - 100 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 20a - - 1.25 v reverse recovery time t rr i sd = 20a, di sd /dt = 100a/ s--70ns reverse recovered charge q rr i sd = 20a, di sd /dt = 100a/ s - - 145 nc rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 15 5 0 25 50 75 100 125 150 10 20 i d , drain current (a) t c , case temperature ( o c) 25 175 t, rectangular pulse duration (s) 10 -5 10 -1 10 0 2 0.1 1 10 -2 z jc , normalized thermal impedance 0.01 10 -4 10 -3 single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 10 1 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 v ds , drain to source voltage (v) 10 100 100 500 1 10 i d , drain current (a) 100 s 10ms 1ms v dss(max) = 30v limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c 1 100ms dc t c = 25 o c t, pulse width (s) 500 100 10 10 -5 10 -4 10 -2 10 -1 10 0 10 1 i dm , peak current (a) transconductance may limit current in this region v gs = 10v v gs = 20v 10 -3 i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature typical performance curves (continued) 1 10 0.001 300 10 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) + 1] starting t j = 25 o c starting t j = 150 o c 0.01 100 0.1 0 20 40 60 0 12345 80 i d , drain current (a) v ds , drain to source voltage (v) v gs = 6v v gs = 10v pulse duration = 80 s t c = 25 o c v gs = 5v 100 v gs = 7v v gs = 20v duty cycle = 0.5% max 0 46 810 2 0 20 40 60 80 i d(on) , on-state drain current (a) v gs , gate to source voltage (v) 175 o c 25 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v 100 -55 o c 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 80 s 200 v gs = 10v, i d = 20a duty cycle = 0.5% max -80 -40 0 40 80 120 160 0.4 0.6 0.8 1.0 1.2 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 200 1.2 1.1 1.0 0.9 0.8 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 200 rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b figure 12. capacitance vs drain to source voltage figure 13. gate charge waveforms for constant gate current test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform typical performance curves (continued) 1800 900 0 0 10 20 30 c, capacitance (pf) 1500 v ds , drain to source voltage (v) 600 c iss c oss c rss 300 1200 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 10 8 6 4 0 v gs , gate to source voltage (v) v dd = 15v 2 18 24 30 0 q g , gate charge (nc) 612 i d = 20a i d = 15a i d = 10a i d = 5a waveforms in descending order: t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b figure 18. switching time test circuit figure 19. resistive switching waveforms test circuits and waveforms (continued) v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b pspice electrical model subckt rfd20n03, RFD20N03SM 2 1 3 ; rev 28 jul 97 ca 12 8 1.3e-9 cb 15 14 1.3e-9 cin 6 8 9.9e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 33.15 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.00e-9 lgate 1 9 3.57e-9 lsource 3 7 4.25e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 5e-4 rgate 9 20 1.24 rldrain 2 5 10 rlgate 1 9 28.6 rlsource 3 7 26.9 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 6.2e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*120),3))} .model dbodymod d (is = 9e-13 rs = 6.4e-3 ikf=7.4 tikf=0.005 n=1.02 trs1 = 3.5e-3 trs2 =-1e-5 cjo = 1.78e-9 tt = 4.0e-8 m = 0.4053) .model dbreakmod d (rs = 0.1 n=3.5 ikf=-1e-3 trs1 = -1e-3 trs2 =1e-6) .model dplcapmod d (cjo = 1.3e-9 is = 1e-30 n = 10 m = 0.62) .model mmedmod nmos (vto = 3.17 kp = 1.3 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.24) .model mstromod nmos (vto = 3.68 kp = 13 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.68 kp = 0.009 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 12.4 rs = 0.1) .model rbreakmod res (tc1 = 8e-4 tc2 = 4.5e-7) .model rdrainmod res (tc1 = 3.5e-2 tc2 = 4.5e-4) .model rslcmod res (tc1 = 1e-3 tc2 = 1e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc = -1.2e-3 tc2 = -2e-5) .model rvtempmod res (tc1 = -3.5e-3 tc2 = 1e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -8.60 voff= -2.50) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.50 voff= -8.60) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.00 voff= 0.30) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.30 voff= 0.00) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rfd20n03, RFD20N03SM
?002 fairchild semiconductor corporation rfd20n03, RFD20N03SM rev. b spice thermal model rev 28 july 97 rfd20n03, RFD20N03SM ctherm1 7 6 9.9e-7 ctherm2 6 5 1.5e-3 ctherm3 5 4 2.2e-3 ctherm4 4 3 5.7e-3 ctherm5 3 2 7.5e-2 ctherm6 2 1 5.4e-1 rtherm1 7 6 8e-3 rtherm2 6 5 2.3e-2 rtherm3 5 4 9.0e-2 rtherm4 4 3 6.9e-1 rtherm5 3 2 6.1e-1 rtherm6 2 1 8.0e-2 rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 1 2 3 4 5 6 7 junction case rfd20n03, RFD20N03SM
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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